Unbalanced electrostatic charge may cause an electrostatic discharge (ESD) if the electrical charge is balanced uncontrolled and fast. For integrated circuits (ICs), an ESD may have significant impact on product quality and production yields. The discharge current of an ESD event may damage or destroy gate oxides, junctions and metallization of ICs. For example, an ESD may occur by a charged body touching an IC or a charged IC touching a grounded surface.
The major ESD models, which are widely used in the industry to model the effect of ESD on ICs, are the human-body model (HBM) and the charge device model (CDM). The HBM simulates the discharge of a charged human body as the human touches a grounded IC. While the stress of an HBM ESD event is mainly determined by the charge that the human body has acquired, the duration of an HBM ESD event is mainly defined by the impedance of the human body. The CDM simulates charging and discharging events that occur in the production equipment and process. A CDM ESD event may occur if there is metal to metal contact in manufacturing. For example, the CDM ESD may occur if a device slides down a shipping tube and hits a metal surface. The CDM addresses the possibility that a charge may reside on the lead frame or package and may discharge through a pin of the electronic device which is grounded. The discharge current will be limited by the parasitic impedance and capacitance of the device only. As a result, a CDM ESD event is much shorter than a HBM ESD event. Since, it may take only one single ESD strike to permanently damage a product, ESD protection is a critical aspect of the design of an electronic device. ESD protection circuits are; for example, known from A. Amerasekera, C. Duvvury, “ESD in Silicon Integrated Circuits”, John Wiley & Sons, Chichester (England), 2002, page 148.
The most simple protection strategy of an input pin is a single stage ESD protection circuit. However, this is less effective than a double stage ESD protection. A secondary stage in the two stage ESD protection circuit, especially, functions to protect sensitive components (e.g. the gate oxide of an input buffer). The secondary protection stage is coupled to the primary protection stage by means of a current limiting component (e.g. a resistor). By limitation of the ESD current that has to be conducted by the secondary protection stage, the ESD induced voltage drop across the secondary protection stage becomes much smaller than the corresponding voltage drop across the first protection stage. This is the reason why a double stage ESD protection is more effective than a single stage ESD protection. Two stage ESD protection circuits may be rather complex in particular for distributed protection stages having the primary and secondary protection stage spaced apart in the IC layout. For optimum performance, the primary protection elements are directly connected to the pin of the IC and the secondary protection elements are placed as close as possible to the component or to a circuit to be protected.
FIG. 1 is a simplified circuit diagram showing an ESD protection circuit, comprising a primary protection stage P1 and a secondary protection stage P2 for protecting an integrated circuit IC against ESD events. Both, the primary protection stage P1 and the secondary protection stage P2 are coupled to a positive supply rail VDD and to a negative supply rail VSS. Both rails are further protected from ESD by the power clamp EPC, which is coupled to the positive supply rail VDD and the negative supply rail VSS. By way of an example only, the input pin IN should be protected. The input pin IN is coupled to a first node S1. A pair of primary rail clamp diodes EHP, ELP is coupled to the first node S1 and to the positive and negative supply rail VDD, VSS, respectively. The primary rail clamp diodes EHP, ELP divert the ESD current that is forced into the IN pad to the power rail VDD, where it is shunted to the power rail VSS by the power clamp EPC. While the voltage difference between the first node S1 and the positive supply rail VDD is indicated by voltage VHP and the voltage difference between the positive power supply rail VDD and the negative power supply rail VSS is indicated by the voltage VPC, the resulting voltage difference between the first node S1 and the negative power supply rail VSS is indicated by the voltage VLP. The first node S1 is decoupled from a second node S2 by a current limiting resistor RS leading to a voltage drop from the first node S1 to the second node S2 of VRS. The remaining voltage drops across both secondary rail clamp diodes EHS, ELS, wherein the voltage between the secondary node S2 and the positive supply rail VDD and the negative supply rail VSS is VHS and VLS, respectively. Due to the current limitation by the resistor RS, the voltages VHS and VLS are much smaller than the corresponding voltages VHP and VLP respectively. Furthermore, the secondary protection elements EHS, ELS can be sized much smaller than the primary protection elements EHP, ELP. If a technology is lacking dedicated diodes, parasitic diodes or other components may be used instead. Double stage ESD protection as shown in FIG. 1 is effective for both HBM ESD protection and CDM ESD protection.
Protection stages comprising a current limiting resistor RS and small protection elements are also used for CDM ESD protection of IC sub circuits or units that have a common signal interface but are supplied by different power supplies. In FIG. 2, there is a simplified circuit diagram showing on an integrated circuit (IC) comprising a first sub circuit SC1 and a second sub circuit SC2. Further, here is a CDM ESD protection stage between the two sub circuits SC1, SC2. FIG. 2 illustrates the principle of ESD protection in an IC having for example a first and a second sub circuit SC1, SC2. By way of an example only, the first sub circuit SC1 is coupled to a first positive supply rail VDD1 and to the common negative supply rail VSS. The output OUT of the first sub circuit SC1 is coupled to the node S2 via the current limiting resistor RS. The second sub circuit SC2 is coupled to a second positive supply rail VDD2, which provides a different supply voltage when compared to the first positive supply rail VDD1. Further, the second sub circuit SC2 is coupled to the common negative supply rail VSS and an input IN of the second sub circuit SC2 is coupled to the node S2.
In order to protect the input IN pin of the second sub circuit SC2 from CDM ESD, the diodes EHS and ELS are connected between node S2 and the positive and negative supply rail VDD2 and VSS, respectively. For optimum performance, the diodes EHS and ELS are placed as close as possible to the input node IN of the second sub circuit SC2 to be protected. If a technology is lacking dedicated diodes, parasitic diodes or other components may be used instead.
Generally speaking, a system is denoted failsafe if failure of any of its components does not cause the complete system to fail. FIG. 3 is a simplified block diagram showing a first integrated circuit or sub circuit (IC1) and a second integrated circuit or sub circuit (IC2) which are both coupled to a common positive supply rail VDD and which are coupled to each other via the nodes OUT and IN. The characteristic “failsafe” or “non-failsafe” can also be applied to ICs and IC pins. An IC node, for example the input node IN of IC2 is denoted “failsafe” if a failure of IC2 does not cause an external component which is connected to the node to fail as well. By way of an example, the input IN of IC2 is not failsafe because it is connected via an internal diode (shown in dashed line) to the supply connecting IC2 to VDD. If the power supply of IC2 fails while the power of IC1 is still maintained, IC2 is indirectly supplied by current that is flowing from IC1 across the internal diode of IC2 to its supply VDD. This current path is drawn in FIG. 2. However, since this parasitic current path was not intended to supply IC2, it may lead to malfunction of IC1 or IC2 or may even cause damage of the ICs.
This problem is even more pronounced if IC1 is supplied by a higher supply voltage than IC2. In this case, IC2 is required to have a voltage tolerant input node IN, in order to avoid large cross currents to flow from the supply of IC1 via its output OUT to the input IN of IC2 and to the supply of IC2.
To avoid malfunction of IC1 and IC2, the input IN of IC2 has to be failsafe. With respect to an ESD protection of IN, this can be established by a primary protection between the input IN and the common supply VSS and a failsafe secondary protection.
The characteristic “failsafe” or “non-failsafe” may also be applied to different sub circuits of a single integrated circuit (IC). Again, reference is made to the example shown in FIG. 2. The input IN of the second sub circuit SC2 is not failsafe because it is connected to the second power supply rail VDD2 via the diode EHS. If the power supply of the second sub circuit SC2 fails while the first power supply VDD1 of the first sub circuit SC1 is still maintained, the second sub circuit SC2 is indirectly supplied by a current that flows from the first sub circuit SC1 across the resistor RS and the diode EHS to the supply VDD2 of SC2.
However, since this parasitic current path was not intended to supply the second sub circuit SC2, it may lead to malfunction of SC1 or SC2 or may even cause damage of the sub circuits SC1, SC2. A similar problem occurs, if the first sub circuit SC1 is supplied by a higher supply voltage than SC2 (i.e. VDD1>VDD2). In this case, the second sub circuit SC2 is required to have a voltage tolerant CDM protection connected to its input IN, in order to avoid permanent cross currents to flow from the first supply rail VDD1 of SC1 via its output OUT to the input IN of the second sub circuit SC2 and to its second supply rail VDD2.